1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, and more specifically to a semiconductor device having active regions of different conductivity types on a semiconductor substrate and a method of manufacturing the device.
2. Description of the Background Art
Conventionally, as an example of a semiconductor device having active regions of different conductivity types on the same semiconductor substrate, a complementary MOS (metal oxide semiconductor) device (hereinbelow simply referred to as "CMOS") is known which is configured by a p-channel MOS transistor and an n-channel MOS transistor.
A conventional CMOS is disclosed, for example, in Japanese Patent No. 2660056 (Japanese Patent Laying-Open No. 3-99464). There is a need for established miniaturization techniques that accompany the higher density and higher degree of integration achieved in a CMOS while maintaining its low power consumption characteristic is maintained.
Structurally, a parasitic bipolar transistor circuit is formed inside a CMOS. Since this bipolar transistor circuit has the same configuration as a thyristor, when the circuit is triggered by a surge or the like from outside, excessive current flows from a power supply terminal, and the so-called latchup phenomenon occurs, where the current continues to flow even after the surge or the like no longer exists. This latchup can destroy the device.
Since the latchup phenomenon more readily occurs as the element is miniaturized, a new structure is required which improves latchup resistance as a CMOS is further miniaturized. One example is a retrograde well structure using an epitaxial layer.
FIG. 18 shows a cross sectional view in which a CMOS inverter is formed upon an epitaxial wafer having a thin epitaxial layer formed on a silicon substrate. In addition, FIG. 18 also shows an equivalent circuit diagram of a parasitic thyristor.
As shown in FIG. 18, a p.sup.- epitaxial layer 3a is formed on the main surface of a p.sup.+ silicon substrate 1a. On the boundary portion between p.sup.- epitaxial layer 3a and silicon substrate 1a, a p-type impurity region 2a is formed. An n-well 4 and a p-well 5 are formed adjacent to each other in p.sup.- epitaxial layer 3a. Moreover, a field oxide film 6 is selectively formed on a surface of p.sup.- epitaxial layer 3a.
A p MOS transistor is formed on n-well 4, and an n MOS transistor is formed on p-well 5. The p MOS transistor is provided with a source region 8a, a drain region 8b, and a gate electrode 7a. The n MOS transistor is provided with a source region 9a, a drain region 9b, and a gate electrode 7b.
Side wall insulating films 12 are formed on the sidewalls of gate electrodes 7a, 7b. Moreover, an n-well contact region 10 is formed on n-well 4, and a p-well contact region 11 is formed on p-well 5.
N-well contact region 10 and source region 8a are connected to a power supply voltage Vcc, gate electrodes 7a, 7b are connected to an input terminal, and drain regions 8b, 9b are connected to an output terminal. Further, source region 9a and p-well contact region 11 are grounded (GND).
In the above-mentioned configuration, a parasitic vertical pnp bipolar transistor 16a with source region 8a serving as an emitter, n-well 4 as a base, and silicon substrate 1a as a collector, and a parasitic lateral npn bipolar transistor 17a with source region 9a serving as an emitter, p-well 5 as a base, and n-well 4 as a collector are formed. A parasitic thyristor is formed from parasitic vertical pnp bipolar transistor 16a and parasitic lateral npn bipolar transistor 17a.
N-well 4 has a retrograde well structure with a bottom portion having a high impurity concentration. Thus, parasitic resistance RW becomes small, and the difference in potential between the base and the emitter of parasitic vertical pnp bipolar transistor 16a also becomes small. Consequently, parasitic vertical pnp bipolar transistor 16a does not turn on easily. In addition, the impurity concentration in the region corresponding to the base of parasitic vertical pnp bipolar transistor 16a is high, causing more recoupling in the base and leading to a lower current amplification factor of parasitic vertical pnp bipolar transistor 16a.
Moreover, the use of p.sup.+ silicon substrate 1a reduces parasitic resistance RS, and the difference in potential between the base and the emitter of parasitic lateral npn bipolar transistor 17a becomes small. Thus, parasitic lateral npn bipolar transistor 17a does not turn on easily. In addition, the impurity concentration in the region corresponding to the base of parasitic lateral npn bipolar transistor 17a becomes high, resulting in more recoupling in the base and leading to a smaller current amplification factor of parasitic lateral npn bipolar transistor 17a.
Therefore, the loop gain of the parasitic thyristor formed by parasitic vertical pnp bipolar transistor 16a and parasitic lateral npn bipolar transistor 17a can be suppressed and latchup resistance may be improved.
In particular, the effect of reduced base resistance of parasitic lateral npn bipolar transistor 17a by the use of p.sup.+ silicon substrate 1a largely contributes to the improvement in latchup resistance. Through the use of p.sup.+ silicon substrate 1a, base resistance of parasitic lateral npn bipolar transistor 17a is reduced to one or two orders of magnitude smaller than that in the case of a typical wafer. As a result, the current required to forward bias the pn junction between the base and the emitter of parasitic lateral npn bipolar transistor 17a becomes extremely large. Since this current is provided by the collector current of parasitic vertical pnp bipolar transistor 16a, parasitic vertical pnp bipolar transistor needs to conduct a large current, resulting in high level injection region operation. Thus, the current amplification factor rapidly decreases, and latchup resistance is improved.
In view of the foregoing, it is preferable to reduce the thickness of p.sup.- epitaxial layer 3a in order to improve the effect of reduced substrate resistance by p.sup.+ silicon substrate 1a. In other words, the effect of an epitaxial wafer becomes more conspicuous as the epitaxial layer becomes thinner.
As the epitaxial layer becomes thinner, however, the following problems may arise.
As shown in FIG. 18, p-type impurity region 2a is formed in the boundary portion between p.sup.+ silicon substrate 1a and p.sup.- epitaxial layer 3a. P-type impurity diffuses from p.sup.+ silicon substrate 1a containing a high concentration of p-type impurity into p.sup.- epitaxial layer 3a to form p-type impurity region 2a. Thus, the concentration of p-type impurity in p-type impurity region 2a gradually changes.
When p.sup.- epitaxial layer 3a is made thinner in order to increase the effect of the epitaxial wafer as described above, p-type impurity region 2a reaches the high concentration region at the bottom portion of n-well 4, changing the distribution of impurity concentration of n-well 4 significantly. Thus, breakdown voltage between p-type source/drain regions 8a, 8b and p.sup.+ silicon substrate 1a decreases and a punch-through phenomenon is more likely to occur.